 rigor
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05d6fadb70
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feature: added ADDR6 connections to the bottom row
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2026-08-02 13:06:41 -05:00 |
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rigor
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ef4c731d42
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feature: got the basic layout done (need to wire in addressing lines)
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2026-08-02 12:58:48 -05:00 |
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rigor
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57cd958212
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fix: corrected an issue with 1 word memory block
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2026-08-02 12:58:21 -05:00 |
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rigor
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2d824dc334
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feature: fixed the 1 word memory block package
- it used to use busses on the package, but that apparently does not work
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2026-08-02 09:45:15 -05:00 |
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rigor
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d38d4cb411
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chore: cleaned up alu reserved space
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2026-07-26 14:24:50 -05:00 |
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rigor
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bd05b901bb
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feature: added docs for ALU instruction set
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2026-07-26 14:18:24 -05:00 |
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rigor
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31de84b5e1
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chore: update component xml file
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2026-07-04 22:50:31 -05:00 |
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rigor
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1a76ee472d
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feature: added 10 bit register component
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2026-07-04 22:38:54 -05:00 |
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rigor
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df25a4b806
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chore: update (and fix) component xml
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2026-07-04 21:13:27 -05:00 |
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rigor
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d55efecef1
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feature: added a 4 to 16 mux
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2026-07-04 19:23:08 -05:00 |
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rigor
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dc9640f6f6
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chore: updated component xml file
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2026-07-04 17:54:00 -05:00 |
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rigor
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70f8898393
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feature: added a 1 bit memory cell
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2026-07-04 17:51:17 -05:00 |
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rigor
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ec4a95a815
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chore: reduced transistor count of overall ALU
finished_alu
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2026-07-04 13:52:19 -05:00 |
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rigor
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bd6e99af7e
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chore: updated xml for component listing
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2026-07-04 13:24:33 -05:00 |
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rigor
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55943611cc
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chore: not sure what this change is, honestly
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2026-07-04 13:23:33 -05:00 |
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rigor
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1a137698cb
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fix: added a weak pull down to the enable pin of the buffer
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2026-07-04 13:22:48 -05:00 |
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rigor
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2a9d5fc960
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feature: debugged the alu
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2026-07-04 13:18:44 -05:00 |
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rigor
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ec60e4f177
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feature: got the NOT pin connected to the command decoder
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2026-07-04 10:43:54 -05:00 |
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rigor
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a0d197c50b
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feature: got the XOR pin connected to the command decoder
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2026-07-04 10:37:44 -05:00 |
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rigor
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3359bbd6e1
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feature: got the NAND pin connected to the command decoder
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2026-07-04 10:28:34 -05:00 |
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rigor
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a05626e61c
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feature: got the OR pin connected to command decoding
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2026-07-04 10:15:48 -05:00 |
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rigor
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898de84779
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feature: got the ADD pin connected to command logic in the ALU
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2026-07-03 15:15:08 -05:00 |
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rigor
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417ae6b12f
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feature: got shift pins set up to be driven by the command word
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2026-07-03 14:25:47 -05:00 |
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rigor
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adbeb6ef52
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feature: did some work on the alu i think
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2026-07-01 21:14:33 -05:00 |
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rigor
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5fd86762bc
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fix: final fix for that version of the ALU
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2026-06-29 23:13:34 -05:00 |
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rigor
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79830a00ba
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fix: another failed push?
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2026-06-29 23:12:28 -05:00 |
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rigor
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6fe92da9fc
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fix: pushed up the wrong thing again?
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2026-06-29 23:11:21 -05:00 |
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rigor
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a68a10ef36
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fix: think I pushed the wrong thing up
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2026-06-29 22:26:08 -05:00 |
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rigor
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4138b8a449
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fix: removed constant voltages
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2026-06-29 22:19:37 -05:00 |
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rigor
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f64c6357b4
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feature: finished ALU v1.0.0 (may need updates to convert microcode to instructions)
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2026-06-29 22:14:37 -05:00 |
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rigor
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b5d05e6a46
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feature: more work on the alu
- got the 1 bit alu made into a component
- started on the 10Bit ALU
- added a 10Bit Buffer
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2026-06-29 00:01:52 -05:00 |
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rigor
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4aca2cda51
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fix: made the inputs and outputs into tunnels so the alu thing can be used as a subcircuit
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2026-06-22 20:24:27 -05:00 |
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rigor
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cd1c75ee67
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chore: turned off constant voltage sources
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2026-06-22 20:17:31 -05:00 |
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rigor
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c0b8efe8e0
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feature: got the first alu card done (I think)
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2026-06-22 20:15:18 -05:00 |
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rigor
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060454fbad
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more work on 1bit alu
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2026-06-21 23:49:54 -05:00 |
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rigor
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aaadeafeae
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added some docs
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2026-06-18 23:31:39 -05:00 |
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rigor
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bd1099f06c
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moved sim file to have the right name
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2026-06-18 23:31:23 -05:00 |
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rigor
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29827484e4
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initial commit
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2026-06-18 23:23:25 -05:00 |
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